Technical Publications I've been involved with

International Test Conference

• 2004 Technical Paper Reviewers

ITRS - International Technology Roadmap for Semiconductors

• 2005
  
• 2006 Update
  
• 2007 Test and Test Equipment

IEEE - Microprocessor Test & Verification

• Program Chair IEEE 8th International Workshop

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression

• IEEE Digital Library
  
• Proceedings of the 12th IEEE European Test Symposium

Patents

• US Patent 6,407,613 B1 Multipurpose Test Chip Input/Output Circuit.
• US Patent 6,867,613 Built-in Self Timing Test Method and Apparatus
• US Patent 7,180,380 B2 Zoned Thermal Monitoring
• US Patent 7,765,0550 B2 Over Temperature Detection Apparatus
• US Patent 7,991,995 B2 Method and Apparatus to Achieve More Level Thermal Gradient

It may seem strange that I have several patents related to thermal issues when I am primarily a Design For Test expert. However, since circuit delays are a function of temperature, understanding the local temperature and/or controlling it during testing are directly related to testing critical timing paths.